ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 112

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.11.6
6.11.7
6.11.8
112
Atmel ATA6612/ATA6613
Pin Change Mask Register 2 – PCMSK2
Pin Change Mask Register 1 – PCMSK1
Pin Change Mask Register 0 – PCMSK0
Initial Value
Read/Write
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16
• Bit 7 – Res: Reserved Bit
• Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Read/Write
Initial Value
Initial Value
Read/Write
When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes
set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump
to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
Each PCINT23..16-bit selects whether pin change interrupt is enabled on the correspond-
ing I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
This bit is an unused bit in the Atmel
Each PCINT14..8-bit selects whether pin change interrupt is enabled on the correspond-
ing I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding
I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.
Bit
Bit
Bit
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16
R/W
PCINT7
7
0
R/W
R
7
–
0
7
0
PCINT14 PCINT13 PCINT12 PCINT11 PCINT10
R/W
PCINT6
6
0
R/W
R/W
6
0
6
0
PCINT5
R/W
5
0
R/W
R/W
5
0
5
0
®
PCINT4
R/W
ATA6612/ATA6613, and will always read as zero.
R/W
4
0
R/W
4
0
4
0
PCINT3
R/W
R/W
R/W
3
0
3
0
3
0
PCINT2
R/W
R/W
R/W
2
0
2
0
2
0
PCINT1
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT0
PCINT8
R/W
R/W
R/W
9111H–AUTO–01/11
0
0
0
0
0
0
PCMSK0
PCMSK1
PCMSK2