ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 132

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Atmel ATA6612/ATA6613
Figure 6-38. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors)
tolerances, it is recommended that maximum frequency of an external clock source is less
than f
An external clock source can not be prescaled.
Figure 6-39. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
PSRSYNC
CS12
CS10
CS11
clk
clk_I/O
T0
T1
I/O
1. The synchronization logic on the input pins (
Tn
clk
/2.5.
Synchronization
I/O
Synchronization
D
LE
Q
ExtClk
Synchronization
D
TIMER/COUNTER1 CLOCK SOURCE
0
< f
Q
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector
clk
Clear
T1
T1/T0)
10-BIT T/C PRESCALER
CS02
CS00
CS01
D
is shown in
Q
(1)
Edge Detector
TIMER/COUNTER0 CLOCK SOURCE
0
Figure
6-38.
clk
T0
Tn_sync
(To Clock
Select Logic)
9111H–AUTO–01/11