ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 198

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.17.3
198
Atmel ATA6612/ATA6613
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and
stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combina-
tions of the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit. Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the
parity bit is inserted after the data bits, before the stop bits. When a complete frame is trans-
mitted, it can be directly followed by a new frame, or the communication line can be set to an
idle (high) state.
inside brackets are optional.
Figure 6-72. Frame Formats
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that chang-
ing the setting of any of these bits will corrupt all ongoing communication for both the Receiver
and Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection
between one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver
ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases
where the first stop bit is zero.
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
St
(n)
P
Sp
IDLE
(IDLE)
Figure 6-72
St
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxDn or TxDn). An IDLE line
must be high.
0
1
illustrates the possible combinations of the frame formats. Bits
2
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
9111H–AUTO–01/11