ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 133

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13.4
6.14
6.14.1
9111H–AUTO–01/11
16-bit Timer/Counter1 with PWM
General Timer/Counter Control Register – GTCCR
Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
•
•
•
•
•
•
•
•
•
•
•
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must
be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
The device-specific I/O Register and bit locations are listed in the
ter Description” on page
The PRTIM1 bit in
enable Timer/Counter1 module.
Read/Write
Initial Value
• Bit 7 – TSM: Timer/Counter Synchronization Mode
• Bit 0 – PSRSYNC: Prescaler Reset
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping
the corresponding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of one
of them advancing during configuration. When the TSM bit is written to zero, the PSRASY
and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting
simultaneously.
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit
is normally cleared immediately by hardware, except if the TSM bit is set. Note that
Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this pres-
caler will affect both timers.
Bit
TSM
R/W
7
0
“Power Reduction Register - PRR” on page 66
R
6
–
0
155.
R
5
–
0
R
4
–
0
Atmel ATA6612/ATA6613
R
3
–
0
R
2
–
0
“16-bit Timer/Counter Regis-
PSRASY
R/W
must be written to zero to
Figure 6-40 on page
1
0
PSRSYNC
R/W
0
0
GTCCR
134.
133