ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 160

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.14.10.7
6.14.10.8
160
Atmel ATA6612/ATA6613
Input Capture Register 1 – ICR1H and ICR1L
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on
the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input
Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the
other 16-bit registers (see
Bit
Read/Write
Initial Value
• Bit 7, 6 – Res: Reserved Bits
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
• Bit 4, 3 – Res: Reserved Bits
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
Initial Value
Read/Write
These bits are unused bits in the Atmel
zero.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-
ally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR1, is set.
These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-
ally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (see
Flag, located in TIFR1, is set.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-
ally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (see
Flag, located in TIFR1, is set.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-
ally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding
Interrupt Vector (see
located in TIFR1, is set.
Bit
R/W
R
7
–
0
7
0
R/W
“Interrupts” on page
R
6
–
0
6
0
“Watchdog Timer” on page
“Accessing 16-bit Registers” on page
ICIE1
R/W
R/W
5
0
5
0
“Interrupts” on page
“Interrupts” on page
R/W
R
4
–
0
4
0
ICR1[15:8]
ICR1[7:0]
®
79) is executed when the ICF1 Flag, located in
ATA6612/ATA6613, and will always read as
R/W
R
3
–
0
3
0
74) is executed when the TOV1 Flag,
OCIE1B
R/W
R/W
79) is executed when the OCF1B
79) is executed when the OCF1A
2
0
2
0
135).
OCIE1A
R/W
R/W
1
0
1
0
TOIE1
R/W
R/W
0
0
0
0
9111H–AUTO–01/11
TIMSK1
ICR1H
ICR1L