ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 192

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.16.2
192
Atmel ATA6612/ATA6613
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
ure 6-67
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing
Table 6-70.
Figure 6-67. SPI Transfer Format with CPHA = 0
Figure 6-68. SPI Transfer Format with CPHA = 1
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
MSB first (DORD = 0)
LSB first (DORD = 1)
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
Table 6-67
SS
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
and
MSB first (DORD = 0)
LSB first (DORD = 1)
Figure
CPOL Functionality
and
6-68. Data bits are shifted out and latched in on opposite edges of the
Table
MSB
LSB
MSB
LSB
6-68, as done below.
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Falling)
Bit 6
Bit 1
Setup (Rising)
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Bit 4
Bit 3
Bit 3
Bit 4
Sample (Falling)
Sample (Rising)
Setup (Falling)
Trailing eDge
Setup (Rising)
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
Bit 1
Bit 6
Bit 1
Bit 6
LSB
MSB
9111H–AUTO–01/11
LSB
MSB
SPI Mode
0
1
2
3
Fig-