ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 131

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13
6.13.1
6.13.2
6.13.3
9111H–AUTO–01/11
Timer/Counter0 and Timer/Counter1 Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Coun-
ters can have different prescaler settings. The description below applies to both
Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
used as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implica-
tions for situations where a prescaled clock is used. One example of prescaling artifacts
occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number
of system clock cycles from when the timer is enabled to the first count occurs can be from 1
to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
tion logic. The synchronized (sampled) signal is then passed through the edge detector.
Figure 6-38 on page 132
zation and edge detector logic. The registers are clocked at the positive edge of the internal
system clock (
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
CLK_I/O
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
T1
When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and
OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is
executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to
page 127
/clk
/256, or f
T0
). The T1/T0 pin is sampled once every system clock cycle by the pin synchroniza-
and
clk
CLK_I/O
I/O
“Waveform Generation Mode Bit Description” on page
). The latch is transparent in the high period of the internal system clock.
/1024.
shows a functional equivalent block diagram of the T1/T0 synchroni-
CLK_I/O
). Alternatively, one of four taps from the prescaler can be
T1
/clk
T
0
pulse for each positive (CSn2:0 = 7) or negative
Atmel ATA6612/ATA6613
127.
CLK_I/O
Table 6-50 on
/8, f
CLK_I/O
/64,
131