ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 267

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.21.2
9111H–AUTO–01/11
Starting a Conversion
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Regis-
ters is blocked. This means that if ADCL has been read, and a conversion completes before
ADCH is read, neither register is updated and the result from the conversion is lost. When
ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When
ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the
interrupt will trigger even if the result is lost.
A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in
Reduction Register - PRR” on page 66
the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in prog-
ress and will be cleared by hardware when the conversion is completed. If a different data
channel is selected while a conversion is in progress, the ADC will finish the current conver-
sion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering
is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source
is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the
ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger
signal, the ADC prescaler is reset and a conversion is started. This provides a method of start-
ing conversions at fixed intervals. If the trigger signal still is set when the conversion
completes, a new conversion will not be started. If another positive edge occurs on the trigger
signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even
if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A con-
version can thus be triggered without causing an interrupt. However, the Interrupt Flag must
be cleared in order to trigger a new conversion at the next interrupt event.
Figure 6-101. ADC Auto Trigger Logic
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADTS[2:0]
DETECTOR
EDGE
by writing a logical zero to it and writing a logical one to
ADATE
Atmel ATA6612/ATA6613
START
CONVERSION
PRESCALER
LOGIC
CLK
ADC
“Power
267