ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 351

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.5
9111H–AUTO–01/11
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
Note:
Mnemonics
FMULSU
MULSU
FMULS
CALL
RCALL
MULS
JMP
ICALL
SBRC
ADIW
FMUL
RJMP
CPSE
SBIW
SUBI
SBCI
ANDI
COM
EOR
NEG
IJMP
RETI
ADD
ADC
SUB
SBC
AND
SBR
CBR
DEC
CLR
SER
MUL
RET
CPC
TST
ORI
INC
CPI
OR
CP
Instruction Set Summary
(1)
(1)
1. These instructions are only available in ATA6613
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,K
Rd,K
Rd,K
Rr, b
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
Description
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Relative Jump
Indirect Jump to (Z)
Direct Jump
Relative Subroutine Call
Indirect Call to (Z)
Direct Subroutine Call
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Operation
Rd
Rd
Rdh:Rdl
Rd
Rd
Rd
Rd
Rdh:Rdl
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
PC
PC
PC
PC
PC
PC
PC
PC
if (Rd = Rr) PC
Rd Rr
Rd Rr C
Rd K
if (Rr(b)=0) PC
Atmel ATA6612/ATA6613
Rd + Rr
Rd + Rr + C
Rd - Rr
Rd - K
Rd - Rr - C
Rd - K - C
Rd
Rd v Rr
Rd
0xFF Rd
0x00 Rd
Rd v K
Rd
Rd + 1
Rd 1
Rd
0xFF
Rd
Rd v K
Z
PC + k + 1
Z
k
STACK
STACK
PC + k + 1
k
Rd
Rd x Rr
Rd x Rr
Rd x Rr
(Rd x Rr)
(Rd x Rr)
(Rd x Rr)
Rdh:Rdl + K
Rdh:Rdl - K
(0xFF - K)
Rd
Rr
K
Rr
Rd
PC + 2 or 3
PC + 2 or 3
<< 1
<< 1
<< 1
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V
Flags
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
I
#Clocks
1/2/3
1/2/3
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
3
3
3
4
4
4
1
1
1
351