ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 164

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.15.3
164
Atmel ATA6612/ATA6613
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
ure 6-54
Figure 6-54. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
source, selected by the Clock Select bits (CS22:0). When no clock source is selected
(CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU,
regardless of whether clk
counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located
in the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Coun-
ter Control Register B (TCCR2B). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A
and OC2B. For more details about advanced counting sequences and waveform generation
(see
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected
by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.
“Modes of Operation” on page
count
direction
clear
clk
top
bottom
shows a block diagram of the counter and its surrounding environment.
Tn
DATA BUS
TCNTn
T2
is present or not. A CPU write overrides (has priority over) all
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalizes that TCNT2 has reached maximum value.
Signalizes that TCNT2 has reached minimum value (zero).
T2
direction
count
). clk
clear
bottom
168).
Control Logic
T2
can be generated from an external or internal clock
top
TOVn
(Int.Req.)
clk
Tn
Prescaler
T2
in the following.
Oscillator
T/C
9111H–AUTO–01/11
clk
I/O
TOSC2
TOSC1
Fig-