ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 230

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.19
6.19.1
6.19.2
6.19.2.1
230
2-wire Serial Interface
Atmel ATA6612/ATA6613
Features
2-wire Serial Interface Bus Definition
TWI Terminology
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The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using
only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external
hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus
lines. All devices connected to the bus have individual addresses, and mechanisms for resolv-
ing bus contention are inherent in the TWI protocol.
Figure 6-77. TWI Bus Interconnection
The following definitions are frequently encountered in this section.
Table 6-87.
The PRTWI bit in
enable the 2-wire Serial Interface.
Term
Master
Slave
Transmitter
Receiver
Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up When AVR is in Sleep Mode
SDA
SCL
TWI Terminology
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
“Power Reduction Register - PRR” on page 66
Device 1
Device 2
Device 3
........
Device n
V
CC
R1
must be written to zero to
R2
9111H–AUTO–01/11