ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 116

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.12.4
6.12.4.1
116
Atmel ATA6612/ATA6613
Output Compare Unit
Force Output Compare
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is
executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The
max and bottom signals are used by the Waveform Generator for handling the special cases
of the extreme values in some modes of operation (see
Figure 6-29
Figure 6-29. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR0x
Compare Registers to either top or bottom of the counting sequence. The synchronization pre-
vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is
disabled the CPU will access the OCR0x directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC0x) bit. Forcing compare match will not set
the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real com-
pare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set,
cleared or toggled).
shows a block diagram of the Output Compare unit.
bottom
FOCn
top
OCRnx
Waveform Generator
WGMn1:0
= (8-bit Comparator)
DATA BUS
COMnX1:0
“Modes of Operation” on page
TCNTn
OCFnx (Int.Req.)
OCnx
9111H–AUTO–01/11
118).