ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 233

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.19.3.4
6.19.3.5
Figure 6-82. Typical Data Transmission
9111H–AUTO–01/11
SDA
SCL
START
Data Packet Format
Combining Address and Data Packets into a Transmission
Addr MSB
1
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START
and STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted
first.
Figure 6-81. Data Packet Format
A transmission basically consists of a START condition, a SLA+R/W, one or more data pack-
ets and a STOP condition. An empty message, consisting of a START followed by a STOP
condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The
Slave extending the SCL low period will not affect the SCL high period, which is determined by
the Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolong-
ing the SCL duty cycle.
Figure 6-82
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
2
SLA+R/W
Transmitter
Aggregate
SDA from
SDA from
SCL from
Receiver
Master
Addr LSB
SDA
SLA+R/W
7
shows a typical data transmission. Note that several data bytes can be transmitted
R/W
8
ACK
9
Data MSB
1
2
Data MSB
1
Atmel ATA6612/ATA6613
Data Byte
2
7
Data Byte
Data LSB
8
7
ACK
Data LSB
9
8
ACK
9
STOP, REPEATED
START or Next
Data Byte
STOP
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