MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 152

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(6) Operation of OVF00 flag
(7) Conflicting operations
150
<1> The OVF00 flag is also set to 1 in the following case.
mode
<2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the
Conflict between the read period of the 16-bit timer capture/compare register (CR00/CR01) and capture trigger
input (CR00/CR01 used as capture register)
Capture trigger input has priority. The data read from CR00/CR01 is undefined.
When any of the following modes is selected: the mode in which clear & start occurs on a match between
TM00 and CR00, the mode in which clear & start occurs at the TI000 pin valid edge, or the free-running
TM00 is counted up from FFFFH to 0000H.
occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.
CR01 capture value
Capture read signal
TM00 count value
CR00 is set to FFFFH
Count clock
Edge input
INTTM01
Count clock
Figure 7-37. Capture Register Data Retention Timing
INTTM00
OVF00
CR00
TM00
Figure 7-36. Operation Timing of OVF00 Flag
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00
X
N
FFFEH
FFFFH
User’s Manual U17890EJ2V0UD
N + 1
FFFFH
Capture
N + 2
0000H
0001H
N + 2
M
Capture, but
read value is
not guaranteed
M + 1
M + 1
M + 2