MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 247

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 00 (BRGC00) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
Similarly, the maximum permissible data frame length can be calculated as follows.
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
The permissible baud rate error between UART00 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
10
11
8
16
24
31
FL = (Brate)
Minimum permissible data frame length: FLmin = 11
Division Ratio (k)
Brate: Baud rate of UART00
k:
FL:
Margin of latch timing: 2 clocks
FLmax = 11
FLmax =
BRmax = (FLmin/11)
BRmin = (FLmax/11)
2. k: Set value of BRGC00
Set value of BRGC00
1-bit data length
1
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
21k – 2
20k
FL
Table 14-5. Maximum/Minimum Permissible Baud Rate Error
FL
k + 2
2
Maximum Permissible Baud Rate Error
k
11
1
1
CHAPTER 14 SERIAL INTERFACE UART00
=
=
FL =
21k + 2
21k
22k
20k
21k
+3.53%
+4.14%
+4.34%
+4.44%
2
User’s Manual U17890EJ2V0UD
2
Brate
Brate
k
2
FL
FL
k
2k
2
Minimum Permissible Baud Rate Error
FL =
21k + 2
2k
3.61%
4.19%
4.38%
4.47%
FL
245