MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 175

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3
(1) Watchdog timer mode register (WDTM)
Address: FF98H
The watchdog timer is controlled by the following two registers.
Symbol
WDTM
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Registers Controlling Watchdog Timer
Notes 1.
WDCS4
WDCS2
7
0
0
0
1
0
0
0
0
1
1
1
1
2.
Note 1
Note 2
After reset: 67H
WDCS3
WDCS1
If “Internal low-speed oscillator cannot be stopped” is specified by an option byte, this cannot
be set. The internal low-speed oscillation clock will be selected no matter what value is written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)
0
1
0
0
1
1
0
0
1
1
6
1
Note 1
Note 2
WDCS0
Internal low-speed oscillation clock (f
X1 input clock (f
Watchdog timer operation stopped
R/W
0
1
0
1
0
1
0
1
5
1
CHAPTER 9 WATCHDOG TIMER
Note 2
User’s Manual U17890EJ2V0UD
f
f
f
f
f
f
f
f
RL
RL
RL
RL
RL
RL
RL
RL
WDCS4
Oscillation clock operation
During Internal Low-speed
/2
/2
/2
/2
/2
/2
/2
/2
XP
11
12
13
14
15
16
17
18
)
4
(8.53 ms)
(17.07 ms)
(34.13 ms)
(68.27 ms)
(136.53 ms)
(273.07 ms)
(546.13 ms)
(1.09 s)
Operation clock selection
WDCS3
3
Overflow time setting
RL
)
WDCS2
2
During X1 input clock operation
f
f
f
f
f
f
f
f
XP
XP
XP
XP
XP
XP
XP
XP
/2
/2
/2
/2
/2
/2
/2
/2
13
14
15
16
17
18
19
20
(409.6 s)
(819.2 s)
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.11 ms)
(26.21 ms)
(52.43 ms)
WDCS1
1
WDCS0
0
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