MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 290

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

at 0000H and 0001H when the reset signal is input.
circuit voltage detection, and each item of hardware is set to the status shown in Table 18-1. Each port pin is high
impedance during reset input or during the oscillation stabilization time just after reset release.
low-speed oscillation clock after the CPU clock operation has stopped for 21/f
watchdog timer is automatically released after the reset, and program execution starts using the internal low-speed
oscillation clock after the CPU clock operation has stopped for 21/f
and LVI circuit power supply detection is automatically released when V
program execution starts using the internal low-speed oscillation clock after the CPU clock operation has stopped for
21/f
288
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
When a high level is input to the RESET pin, the reset is released and program execution starts using the internal
Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin.
RL
(s) (see CHAPTER 19 POWER-ON-CLEAR CIRCUIT and CHAPTER 20 LOW-VOLTAGE DETECTOR).
2. During reset input, the X1 input clock and internal low-speed oscillation clock stop
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
oscillating.
input. However, the port pins become high-impedance.
CHAPTER 18 RESET FUNCTION
User’s Manual U17890EJ2V0UD
RL
(s) (see Figures 18-2 to 18-4). Reset by POC
DD
> V
POC
RL
or V
(s). A reset generated by the
DD
> V
LVI
after the reset, and