MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 337

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
AND1
OR1
XOR1
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operands
CHAPTER 24 INSTRUCTION SET
User’s Manual U17890EJ2V0UD
Bytes
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
Note 1
6
4
6
6
4
6
6
4
6
4
4
6
4
4
6
2
2
2
Clocks
Note 2
7
7
7
6
8
6
8
7
7
7
7
7
7
7
7
7
8
6
8
6
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
1
0
CY
1
0
1
0
1
0
1
0
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CPU
1
0
) selected by the processor clock
Operation
Z AC CY
Flag
335
1
0