MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 242

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

240
R
X
D00/P13
(e) Reception error
(f) Noise filter of receive data
Parity error
Framing error
Overrun error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 00 (ASIS00) is set as a result of data
reception, a reception error interrupt request (INTSRE00) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS00 in the
reception error interrupt servicing (INTSRE00) (see Figure 14-3).
The contents of ASIS00 are reset to 0 when ASIS00 is read.
The R
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Base clock
Reception Error
X
D00 signal is sampled using the base clock output by the prescaler block.
In
The parity specified for transmission does not match the parity of the receive data.
Stop bit is not detected.
Reception of the next data is completed before data is read from receive buffer
register 00 (RXB00).
CHAPTER 14 SERIAL INTERFACE UART00
Table 14-3. Cause of Reception Error
Figure 14-10. Noise Filter Circuit
Q
User’s Manual U17890EJ2V0UD
Internal signal A
Match detector
Cause
In
LD_EN
Q
Internal signal B