MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 332

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.2 Operation List
330
8-bit data
transfer
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
MOV
XCH
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
control register (PCC).
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 24 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U17890EJ2V0UD
Bytes
2
2
2
3
2
2
1
1
1
1
1
2
1
1
2
3
3
1
1
2
2
3
3
1
2
2
1
1
1
2
3
2
2
Note 1
4
6
2
2
4
4
8
8
4
4
4
4
8
8
6
6
6
6
2
4
8
4
4
8
8
8
Clocks
Note 2
10
10
10
10
7
7
5
5
5
5
9
9
7
5
5
5
5
5
5
9
9
7
7
7
7
6
6
6
6
r
(saddr)
sfr
A
r
A
(saddr)
A
sfr
A
(addr16)
PSW
A
PSW
A
(DE)
A
(HL)
A
(HL + byte)
A
(HL + B)
A
(HL + C)
A
A
A
A
A
A
A
A
A
byte
A
r
(saddr)
sfr
(addr16)
PSW
(DE)
(HL)
(HL + byte)
(HL + B)
(HL + C)
r
(saddr)
(sfr)
(addr16)
(DE)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
A
A
A
byte
A
byte
A
A
A
A
CPU
A
) selected by the processor clock
Operation
Z AC CY
Flag