MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 279

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.1.2 Registers controlling standby function
(1) Oscillation stabilization time counter status register (OSTC)
The standby function is controlled by the following two registers.
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
This is the status register of the X1 input clock oscillation stabilization time counter. If the internal low-speed
oscillation clock is used as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Reset release (reset by RESET input, POC, LVI, and WDT), the STOP instruction, and MSTOP (bit 7 of MOC
register) = 1 clear OSTC to 00H.
Address: FFA3H
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Symbol
OSTC
Figure 17-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
Remark f
MOST11
7
0
1
1
1
1
1
After reset: 00H
4. OSTC cannot be used when the internal high-speed oscillation clock is selected
2. The oscillation stabilization time counter counts only during the oscillation
3. The wait time when STOP mode is released does not include the time after
X
: X1 input clock oscillation frequency
as the high-speed system clock by using the option byte.
Secure wait time (350 s) by software.
MOST13
remain 1.
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal low-speed oscillation clock is being used as the CPU clock, set
the oscillation stabilization time as follows.
Note, therefore that only the statuses during the oscillation stabilization time set
by OSTS is set to OSTC after STOP mode is released.
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
6
0
0
1
1
1
1
Desired OSTC oscillation stabilization time
set by OSTS
X1 pin voltage
waveform
CHAPTER 17 STANDBY FUNCTION
R
MOST14
User’s Manual U17890EJ2V0UD
5
0
0
0
1
1
1
STOP mode release
MOST11
MOST15
4
0
0
0
1
1
a
MOST16
MOST13
3
0
0
0
0
1
2
2
2
2
2
MOST14
11
13
14
15
16
Oscillation stabilization time status
/f
/f
/f
/f
/f
X
X
X
X
X
2
min. 102.4 s min. 128 s min.
min. 409.6 s min. 512 s min.
min. 819.2 s min. 1.02 ms min.
min. 1.64 ms min. 2.04 ms min.
min. 3.27 ms min. 4.09 ms min.
Oscillation stabilization time
f
X
= 20 MHz
MOST15
1
f
X
MOST16
= 16 MHz
0
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