MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 240

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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238
1. Stop bit length: 1
2. Stop bit length: 2
(c) Transmission
The T
register 00 (ASIM00) is set to 1. If bit 6 (TXE00) of ASIM00 is then set to 1, transmission is enabled.
Transmission can be started by writing transmit data to transmit shift register 00 (TXS00). The start bit,
parity bit, and stop bit are automatically appended to the data.
If bit 6 (TXE00) of ASIM00 is then set to 1, transmission is enabled.
Transmission can be started by writing transmit data to transmit shift register 00 (TXS00) at least two base
clock (f
data.
When transmission is started, the start bit is output from the T
order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM00 are
appended and a transmission completion interrupt request (INTST00) is generated.
Transmission is stopped until the data to be transmitted next is written to TXS00.
Figure 14-8 shows the timing of the transmission completion interrupt request (INTST00). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS00, do not write the next transmit data before the
T
T
X
X
D00 (output)
D00 (output)
INTST00
INTST00
X
D00 pin outputs a high level when bit 7 (POWER00) of asynchronous serial interface operation mode
XCLK0
transmission completion interrupt signal (INTST00) is generated.
) after setting TXE00 = 1. The start bit, parity bit, and stop bit are automatically appended to the
Figure 14-8. Transmission Completion Interrupt Request Timing
Start
Start
CHAPTER 14 SERIAL INTERFACE UART00
D0
D0
User’s Manual U17890EJ2V0UD
D1
D1
D2
D2
D6
D6
X
D00 pin, followed by the rest of the data in
D7
D7
Parity
Parity
Stop
Stop