MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 287

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MC-78F0712-KIT

Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Datasheets

Specifications of MC-78F0712-KIT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
(a) Release by unmasked interrupt request
Standby release signal
Standby release signal
When an unmasked interrupt request is generated, the STOP mode is released.
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby
Internal low-speed
oscillation clock
Status of CPU
X1 input clock
Status of CPU
2. When the STOP instruction is executed while the internal low-speed oscillation clock is stopped
3. f
mode is acknowledged.
(RSTOP = 1), the internal low-speed oscillation clock is kept stopped after the STOP mode is
released.
(2) When internal low-speed oscillation clock is used as CPU clock
RL
Figure 17-6. STOP Mode Release by Interrupt Request Generation
: Internal low-speed oscillation clock oscillation frequency
Operating mode
(Internal low-speed
(X1 input clock)
Operating mode
oscillation clock)
Oscillates
(1) When X1 input clock is used as CPU clock
instruction
STOP
instruction
CHAPTER 17 STANDBY FUNCTION
STOP
User’s Manual U17890EJ2V0UD
Oscillation stopped
STOP mode
STOP mode
Oscillation stabilization time (set by OSTS)
Oscillates
Operation
Oscillation stabilization wait
stopped
(21/f
(HALT mode status)
RL
)
(set by OSTS)
Oscillates
(Internal low-speed oscillation clock)
Wait
Operating mode
After the oscillation
Operating mode
(X1 input clock)
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