MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 208

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(2) Analog input channel specification register (ADS)
206
Notes 1. The EGA1 and EGA0 bits are valid only when the hardware trigger mode (TRG bit = 1) and external
Cautions 1. Be sure to clear bit 2 and 3 of ADS to 0.
This register specifies the input port of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
2. The ADTMD bit is valid only when the hardware trigger mode (TRG bit = 1) is selected.
2. If data is written to ADS, a wait cycle is generated. For details, see CHAPTER 27 CAUTIONS
trigger mode (ADTRG pin input: ADTMD bit = 1) are selected.
Symbol
Address: FF6DH
FOR WAIT.
Figure 13-5. Format of Analog Input Channel Specification Register (ADS)
ADS
ADTMD
EGA1
ADS2
EGA1
TRG
0
0
1
1
0
1
0
0
0
0
1
0
1
7
Note 1
Note 2
EGA0
After reset: 00H
External trigger (ADTRG pin input)
Timer trigger (INTADTR signal generated)
Software trigger mode
Hardware trigger mode
EGA0
ADS1
6
0
1
0
1
0
0
1
1
Note 1
CHAPTER 13 A/D CONVERTER
No edge detection
Falling edge
Rising edge
Both rising and falling edges
ADS0
User’s Manual U17890EJ2V0UD
TRG
Specification of external trigger signal (ADTRG) edge
0
1
0
1
5
Specification of hardware trigger mode
R/W
ADTMD
ANI0
ANI1
ANI2
ANI3
Setting prohibited
Analog input channel specification
Trigger mode selection
4
Select mode
0
3
ADS2
2
ANI0
ANI0, ANI1
ANI0 to ANI2
ANI0 to ANI3
Setting prohibited
ADS1
Scan mode
1
ADS0
0