MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 91

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
f
RL
A status transition diagram of this product is shown in Figure 5-12, and the relationship between the operation
: Oscillation stopped
CPU clock: f
f
Notes 1.
XP
: Oscillating
Status 4
(1) When “Internal low-speed oscillator can be stopped by software” is selected by option byte
2.
3.
4.
5.
XP
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
In the case of the X1 clock, check the oscillation stabilization time status using the oscillation
stabilization time counter status register (OSTC) before shifting from status 2 to status 3 after reset
and STOP are released. In the case of the internal high-speed oscillation clock, secure wait time
(350 s) by software.
When shifting from status 2 to status 1, make sure that MCS is 0.
When “Internal low-speed oscillator can be stopped by software” is selected by an option byte, the
watchdog timer stops operating in the HALT and STOP modes, regardless of the source clock of the
watchdog timer. However, oscillation of internal low-speed oscillator does not stop even in the HALT
and STOP modes if RSTOP = 0.
All reset sources (RESET input, POC, LVI, and WDT)
RSTOP = 1
RSTOP = 0
instruction
Interrupt
HALT
instruction
STOP
Interrupt
Note 1
Figure 5-12. Status Transition Diagram (1/2)
CPU clock: f
f
f
XP
RL
: Oscillating
: Oscillating
Status 3
STOP
instruction
Interrupt
CHAPTER 5 CLOCK GENERATOR
User’s Manual U17890EJ2V0UD
XP
Interrupt
HALT
instruction
MCM0 = 1
MCM0 = 0
STOP
HALT
instruction
Interrupt
Note 4
Note 4
STOP
Note 2
CPU clock: f
f
f
XP
RL
Interrupt
: Oscillating
Status 2
: Oscillating
HALT
instruction
HALT instruction
RL
instruction
Interrupt
Reset
MSTOP = 1
Reset release
STOP
MSTOP = 0
Note 5
Interrupt
Note 3
f
XP
: Oscillation stopped
CPU clock: f
f
RL
: Oscillating
Status 1
RL
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