MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 198

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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12.3 Register for Controlling Hi-Z Output Controller
196
(1) High-impedance output control register 0 (HZA0CTL0)
The HZA0CTL0 register is an 8-bit register that controls the high-impedance state of the output buffer of the
TW0TO0 to TW0TO5 pins.
This register is set by using a 1-bit or 8-bit manipulation instruction. The HZA0DCF0 bit, however, is a read-
only bit and nothing can be written to it even if the write operation is performed.
Reset input sets this register to 00H.
The same value can always be written to the HZA0CTL0 register by using software.
HZA0CTL0
Figure 12-2. Format of High-impedance Output Control Register 0 (1/2)
After reset: 00H
HZA0DCE0
HZA0DCE0
HZA0DCM0
HZA0DCN0
HZA0DCT0
Clear the HZA0DCE0 bit to 0 when rewriting the HZA0DCM0 bit.
Clear the HZA0DCE0 bit to 0 when rewriting the HZA0DCN0 and HZA0DCP0 bits.
Setting the HZA0DCT0 bit to 1 is invalid if a level indicating an abnormality
The HZA0DCT0 bit is a software trigger bit and is always 0 when it is read.
Setting the HZA0DCT0 bit to 1 is invalid when the HZA0DCE0 bit = 0.
Setting the HZA0DCT0 and HZA0DCC0 bits simultaneously to 1 is prohibited.
(detected according to the setting of the HZA0DCN0 and HZA0DCP0 bits)
is input to the TW0TOFFP pin.
0
1
0
1
0
0
1
1
0
1
7
CHAPTER 12 Hi-Z OUTPUT CONTROLLER
HZA0DCM0 HZA0DCN0 HZA0DCP0 HZA0DCT0 HZA0DCC0
HZA0DCP0
Disables high-impedance output control operation. Target pins can output their signals.
Enables high-impedance output control operation.
Setting of the HZA0DCC0 bit is valid regardless of the TW0TOFFP pin input.
Setting of the HZA0DCC0 bit is invalid while the TW0TOFFP holds a level
at which an abnormality has been detected (active level).
No operation
Software makes a target pin go into a high-impedance state and the
HZA0DCF0 bit is set to 1.
R/W
0
1
0
1
6
Condition of clearing high-impedance state by HZA0DCC0 bit
User’s Manual U17890EJ2V0UD
No valid edge
(Setting the HZA0DCF0 bit by the TW0TOFFP pin input is disabled.)
The rising edge of the TW0TOFFP pin input is valid.
(Abnormality is detected when the high level is input.)
The falling edge of the TW0TOFFP pin input is valid.
(Abnormality is detected when the low level is input.)
Setting prohibited
Address: FF69H
5
Specification of input edge of TW0TOFFP pin
High-impedance output trigger bit
High-impedance output control
4
3
2
1
0
HZA0DCF0
0