MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 234

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(3) Baud rate generator control register 00 (BRGC00)
232
Address: FF71H After reset: 1FH R/W
BRGC00
Notes 1.
Symbol
This register selects the base clock of serial interface UART00 and the division value of the 5-bit counter.
BRGC00 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
2.
Be sure to set the base clock so that the following condition is satisfied.
When the TM50 output is selected as the count clock, observe the following.
It is not necessary to enable the TO50 pin as a timer output pin (bit 00 (TOE50) of the TMC register
may be 0 or 1), regardless which mode.
MDL004
TPS001
TPS001
V
Set the clock so that the duty will be 50% and start the operation of 8-bit timer/event counter 50 in
advance.
Enable the timer F/F inversion operation (TMC501 = 1) and start the operation of 8-bit timer/event
counter 50 in advance.
DD
7
0
0
1
1
0
0
0
0
1
1
1
1
1
Figure 14-4. Format of Baud Rate Generator Control Register 00 (BRGC00)
PWM mode (TMC506 = 1)
Clear & start mode entered on match of TM50 and CR50 (TMC506 = 0)
= 4.0 to 5.5 V: Base clock
MDL003
TPS000
TPS000
6
0
1
0
1
0
1
1
1
1
1
1
1
1
CHAPTER 14 SERIAL INTERFACE UART00
TM50 output
f
f
f
X
X
X
MDL002
/2
/2
/2
2
4
6
5
0
0
0
0
0
1
1
1
1
User’s Manual U17890EJ2V0UD
10 MHz
Note 2
MDL004
MDL001
4
0
0
1
1
0
0
1
1
Base clock (f
5 MHz
1.25 MHz
312.5 kHz
MDL003
MDL000
At f
3
0
1
0
1
0
1
0
1
XP
XCLK0
= 20 MHz
) selection
10
27
28
29
30
31
MDL002
k
8
9
2
Setting prohibited
f
f
f
f
f
f
f
f
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
Selection of 5-bit counter
Note 1
/8
/9
/10
/27
/28
/29
/30
/31
4MHz
1 MHz
250 kHz
MDL001
output clock
At f
1
XP
= 16 MHz
MDL000
0