MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 219
MC-78F0712-KIT
Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Specifications of MC-78F0712-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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(2) Power-fail detection function (when PFEN = 1)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail
comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin
specified by the analog input channel specification register (ADS) is started.
When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion
result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an
interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM.
<1> When PFEN = 1 and PFCM = 0
<2> When PFEN = 1 and PFCM = 1
Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is
Remark n = 0 to 3
The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only
generated when the higher 8 bits of ADCR
The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only
generated when the higher 8 bits of ADCR < PFT.
replaced by the next conversion result.
A/D conversion
Higher 8 bits
(PFEN = 1)
of ADCR
Figure 13-14. Power-Fail Detection (When PFEN = 1 and PFCM = 0)
INTAD
PFT
First conversion
ANIn
CHAPTER 13 A/D CONVERTER
Condition match
User’s Manual U17890EJ2V0UD
PFT.
ANIn
80H
80H
Note
ANIn
7FH
ANIn
80H
217
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