MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 232

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
230
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE00) of asynchronous serial
Cautions 1. At startup, set POWER00 to 1 and then set TXE00 to 1. To stop the operation, clear TXE00 to
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 00 (ASIM00) (2/2)
interface reception error status register 00 (ASIS00) is not set and the error interrupt does not occur.
2. At startup, set POWER00 to 1 and then set RXE00 to 1. To stop the operation, clear RXE00 to
3. Set POWER00 to 1 and then set RXE00 to 1 while a high level is input to the RxD00 pin. If
4. TXE00 and RXE00 are synchronized by the base clock (f
5. Set transmit data to TXS00 at least two base clock (f
6. Clear the TXE00 and RXE00 bits to 0 before rewriting the PS001, PS000, and CL00 bits.
7. Make sure that TXE00 = 0 when rewriting the SL00 bit. Reception is always performed with
8. Be sure to set bit 0 to 1.
PS001
CL00
SL00
0, and then clear POWER00 to 0.
0, and then clear POWER00 to 0.
POWER00 is set to 1 and RXE00 is set to 1 while a low level is input, reception is started.
transmission or reception again, set TXE00 or RXE00 to 1 at least two clocks of base clock
after TXE00 or RXE00 has been cleared to 0. If TXE00 or RXE00 is set within two clocks of
base clock, the transmission circuit or reception circuit may not be initialized.
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL00 bit.
0
0
1
1
0
1
0
1
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
PS000
0
1
0
1
CHAPTER 14 SERIAL INTERFACE UART00
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
User’s Manual U17890EJ2V0UD
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
XCLK0
) after setting TXE00 = 1.
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
XCLK0
) set by BRGC00. To enable
Reception operation
Note