MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 78

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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(1) Processor clock control register (PCC)
76
Caution Be sure to set bit 3 to 7 to 0.
Remark
The PCC register is used to set the CPU clock division ratio.
The PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0 series.
relationship between the CPU clock (f
Notes 1. The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock
f
f
f
f
f
Address: FFFBH
XP
XP
XP
XP
XP
Symbol
CPU Clock (f
/2
/2
/2
/2
PCC
2
3
4
2. The option byte is used to select the high-speed system clock (X1 clock or internal high-speed
3. Setting prohibited.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
f
XP
:
(high-speed system clock or internal low-speed oscillation clock) (see Figure 5-5).
oscillation clock).
CPU
PCC2
Main system clock oscillation frequency
)
7
0
0
0
0
0
1
After reset: 00H
Figure 5-2. Format of Processor Clock Control Register (PCC)
0.1 s
0.2 s
0.4 s
0.8 s
1.6 s
At 20 MHz Operation
Other than above
PCC1
6
0
0
0
1
1
0
X1 Clock
R/W
CHAPTER 5 CLOCK GENERATOR
CPU
PCC0
High-speed System Clock
) and minimum instruction execution time is as shown in the Table 5-2.
User’s Manual U17890EJ2V0UD
5
0
0
1
0
1
0
0.125 s
0.25 s
0.5 s
1.0 s
2.0 s
At 16 MHz Operation
Note 2
Minimum Instruction Execution Time: 2/f
f
f
f
f
f
Setting prohibited
XP
XP
XP
XP
XP
/2
/2
/2
/2
2
3
4
4
0
Note 1
0.25 s
0.5 s
1.0 s
2.0 s
4.0 s
Oscillation Clock
Internal High-speed
3
0
CPU clock (f
At 8 MHz (TYP.)
f
f
f
f
f
X
X
X
X
X
Operation
/2 or f
/2
/2
/2
or f
2
3
4
MCM0 = 1
or f
or f
or f
RH
PCC2
RH
RH
RH
RH
/2
2
CPU
/2
/2
/2
2
3
4
Note 2
) selection
CPU
PCC1
Oscillation Clock
Internal Low-speed
f
f
Setting prohibited
Setting prohibited
Setting prohibited
At 240 kHz (TYP.)
1
RL
RL
/2
Operation
MCM0 = 0
16.6 s
8.3 s
Note 3
Note 3
Note 3
Therefore, the
PCC0
0
Note 1