MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 106

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Cache
If the referenced address is mapped into the SRAM module, that module services the request in a single
cycle. In this case, data accessed from the cache is simply discarded and no external memory references
are generated. If the address is not mapped into the SRAM space, the cache handles the request in the
normal fashion.
4.3.2
For every memory reference the ColdFire core or the debug module generates, a set of effective attributes
is determined based on the address and the access control registers (ACRs). This set of attributes includes
the cacheable/non-cacheable definition, the precise/imprecise handling of operand write, and the
write-protect capability.
In particular, each address is compared to the values programmed in the ACRs. If the address matches one
of the ACR values, the access attributes from that ACR are applied to the reference. If the address does
not match either ACR, then the default value defined in the cache control register (CACR) is used. The
specific algorithm is as follows:
if (address == ACR0_address including mask)
4.3.3
The cache does not monitor data references for accesses to cached instructions. Therefore, software must
maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code
segments if instructions are cached.
The cache invalidation can be performed in several ways. For the instruction- or data-only configurations,
setting CACR[CINV] forces the entire cache to be marked as invalid. The invalidation operation requires
128
For the split configuration, CACR[INVI] and CACR[INVD] can be used in addition to CACR[CINV] to
clear the entire cache, only the instruction half, or only the data half. Any subsequent fetch accesses are
postponed until the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed,
the cache entry defined by bits [
is cleared. For the split data/instruction cache configuration, software directly controls bit
whether an instruction cache or data cache line is being accessed.
These invalidation operations can be initiated from the ColdFire core or the debug module.
4.3.4
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected
by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting
CACR[CINV] before the cache can be enabled.
4-8
else if (address == ACR1_address including mask)
cycles because the cache sequences through the entire tag array, clearing a single location each cycle.
Effective Attributes = ACR0 attributes
else Effective Attributes = CACR default attributes
Memory Reference Attributes
Cache Coherency and Invalidation
Reset
Effective Attributes = ACR1 attributes
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
10
:4] of the source address register is invalidated, provided CACR[CPDI]
Freescale Semiconductor
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that selects