MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 243

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 14-1
Freescale Semiconductor
Address
Data
Byte strobes
Output enable
Transfer acknowledge
Transfer error
acknowledge
Read/Write
Transfer size
Transfer start
Transfer in progress
Chip selects
SDRAM row
address strobe
SDRAM column
address strobe
lists the external signals grouped by functionality.
Signal Name
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
A[23:0]
D[31:0]
BS[3:0]
OE
TA
TEA
R/W
SIZ[1:0]
TS
TIP
CS[6:0]
SRAS
SCAS
Abbreviation
Table 14-1. MCF5282 Signal Description
External Memory Interface
SDRAM Controller Signals
Define the address of external byte,
word, longword, and 16-byte burst
accesses.
Data bus. Provide the general purpose
data path between the MCU and all
other devices.
data bus.
Indicates when an external device can
drive data on the bus.
Indicates that the external data
transfer is complete and should be
asserted for one clock.
Indicates that an error condition exists
for the bus transfer.
Indicates the direction of the data
transfer on the bus.
Specify the data access size of the
current external bus reference.
Asserted during the first CLKOUT
cycle of a transfer when address and
attributes are valid.
Asserted to indicate that a bus transfer
is in progress. Negated during idle bus
cycles.
Programmed for a base address
location and for masking addresses,
port size and burst capability
indication, wait state generation, and
internal/external termination.
SDRAM synchronous row address
strobe.
SDRAM synchronous column address
strobe.
Define the byte lane of data on the
NOTE
Function
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
Signal Descriptions
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14-19
14-19
14-19
14-19
14-20
14-20
14-20
14-20
14-21
14-21
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Page
14-3