MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 380

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

General Purpose Timer Modules (GPTA and GPTB)
20.5.12 GPT Flag Register 1 (GPTFLG1)
20.5.13 GPT Flag Register 2 (GPTFLG2)
20-12
Bit(s)
Bit(s)
2–0
7–4
3–0
Address
Address
Reset
Reset
Field
Field
R/W
R/W
Name
Name
PRn
CnF
—
TOF
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
7
Table 20-14. GPTSCR2 Field Descriptions (continued)
7
Prescaler bits. Select the prescaler divisor for the GPT counter.
000 Prescaler divisor 1
001 Prescaler divisor 2
010 Prescaler divisor 4
011 Prescaler divisor 8
100 Prescaler divisor 16
101 Prescaler divisor 32
110 Prescaler divisor 64
111 Prescaler divisor 128
Note: The newly selected prescaled clock does not take effect until the next
synchronized edge of the prescaled clock when the clock count transitions to 0x0000.)
Figure 20-14. GPT Flag Register 1 (GPTFLG1)
Reserved, should be cleared.
Channel flags. A channel flag is set when an input capture or output compare event
occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0
has no effect).
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read
or an output compare write clears the corresponding channel flag. When a channel
flag is set, it does not inhibit subsequent output compares or input captures.
Figure 20-15. GPT Flag Register 2 (GPTFLG2)
Table 20-15. GPTFLG1 Field Descriptions
6
6
—
IPSBAR + 0x1A_000E, 0x1B_000E
IPSBAR + 0x1A_000F, 0x1B_000F
5
5
4
0000_0000
0000_0000
4
R/W
R/W
Description
3
Description
—
3
CF
Freescale Semiconductor
0
0