MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 492

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

FlexCAN
25.5.4
Table 25-12
25.5.5
Table 25-13
25-22
Bits
7–6
Bits
7–0
Address
Address
Reset
Reset
Field
Field
R/W
R/W
Prescaler Divide Register (PRESDIV)
FlexCAN Control Register 2 (CANCTRL2)
Name
PRES_DIV Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency and
RJW
describes the PRESDIV fields.
describes the CANCTRL2 fields.
Name
Resynchronization jump width. The RJW field defines the maximum number of time quanta a bit time
may be changed during resynchronization. The valid programmed values are 0 through 3.
The resynchronization jump width is calculated as follows:
7
7
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same frequency
as the system clock. The valid programmed values are 0 through 255. See
Timing” for more information.
RJW
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 25-10. FlexCAN Control Register 2 (CANCTRL2)
Figure 25-9. Prescaler Divide Register (PRESDIV)
6
Table 25-13. CANCTRL2 Field Descriptions
Table 25-12. PRESDIV Field Descriptions
5
IPSBAR + 0x1C_0008
IPSBAR + 0x1C_0009
PSEG1
S-clock
PRES_DIV
0000_0000
0000_0000
Description
R/W
Description
R/W
=
-------------------------------------------- -
2 PRESDIV + 1
(
3
f sys
)
2
PSEG2
Section 25.4.8, “Bit
Freescale Semiconductor
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