MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 225

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 13
External Interface Module (EIM)
This chapter describes data-transfer operations, error conditions, and reset operations.
“Synchronous DRAM Controller
13.1
The following list summarizes bus operation features:
13.2
Table 13-1
Freescale Semiconductor
•
•
•
•
•
Up to 24 bits of address and 32 bits of data
Access 8-, 16-, and 32-bit data port sizes
Generates byte, word, longword, and line-size transfers
Burst and burst-inhibited transfer support
Optional internal termination for external bus cycles
Features
Bus and Control Signals
summarizes the bus signals described in
1
These signals change after the falling edge. In the Electrical Specifications, these signals are
specified off of the rising edge because CLKIN is squared up internally.
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used
for the bus.
Signal Name
CS[6:0]
SIZ[1:0]
A[23:0]
D[31:0]
OE
BS
R/W
TIP
TS
TA
1
1
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Address bus
Byte selects
Chip selects
Data bus
Output enable
Read/write
Transfer size
Transfer acknowledge
Transfer in progress
Transfer start
Table 13-1. ColdFire Bus Signal Summary
Module,” describes DRAM cycles.
Description
NOTE
Chapter 14, “Signal
I/O
I/O
O
O
O
O
O
O
O
O
I
Descriptions”.
Rising
Falling
Falling
Rising
Falling
Rising
Rising
Rising
Rising
Rising
CLKOUT Edge
Chapter 15,
13-1