MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 290

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Synchronous DRAM Controller Module
15.2.4.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency,
through the SDRAM component’s mode register. CAS latency is a function of the speed of the SDRAM
and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3.
Although the DRAM controller supports bursting operations, it does not use the bursting features of the
SDRAMs. Because the processor can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed
burst length in the SDRAMs mode register becomes problematic. Therefore, the processor DRAM
controller generates the burst cycles rather than the SDRAM device. Because the processor generates a
new address and a
should be set either not to burst or to a burst length of one. This allows bursting to be controlled by the
processor.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the base
address and mask registers must be set to the appropriate configuration to allow the mode register to be
set. Note that improperly set DMR mask bits may prevent access to the mode register address. Thus, the
user should determine the mapping of the mode register address to the processor address bits to find out if
an access is blocked. If the DMR setting prohibits mode register access, the DMR should be reconfigured
to enable the access and then set to its necessary configuration after the
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the
SDRAM address space generates the
selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed
for the
of that access needs the correct mode programming information on the correct address bits.
Figure 15-10
15.3
This example interfaces a 512K x 32-bit x 4 bank SDRAM component to processor operating at 40 MHz.
Table 15-25
15-18
MRS
SDRAM Example
command. The
lists design specifications for this example.
shows the
READ
MRS
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
or
MRS
WRITE
SD_CS[1] or [0]
Figure 15-10. Mode Register Set (
command, which occurs in the first clock of the bus cycle.
SRAS, SCAS
access can be a read or write. The important thing is that the address output
CLKOUT
DRAMW
command for each transfer within the burst, the SDRAM mode register
D[31:0]
A[23:0]
MRS
command to that SDRAM. The address of the access should be
MRS
MRS
) Command
MRS
command executes.
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