MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 749

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix C
Index
A
A/D converter
Acknowledge error (ACKERR) 25-26
Address variant 30-4
Analog inputs 28-66
Analog power signals 28-56
Analog reference signals 28-56
Analog supply
Async inputs signal timing 33-23
B
BDM
Freescale Semiconductor
bias 28-34
block diagram 28-32
channel decode 28-33
comparator 28-33
cycle times 28-32
multiplexer 28-33
operation 28-31
sample buffer 28-33
state machine 28-34
successive approximation register (SAR) 28-34
filtering 28-61
grounding 28-61
see debug
commands
CPU halt 30-16
operation with processor 30-38
DUMP 30-27
FILL 30-29
format 30-20
GO 30-31
NOP 30-31
RAREG/RDREG 30-23
RCREG 30-31
RDMREG 30-35
READ 30-24
sequence diagrams 30-21
summary 30-19
WAREG/WDREG 30-23
WCREG 30-34
WDMREG 30-36
WRITE 30-26
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Bit error (BITERR) 25-26
Bit stuff error (STUFFERR) 25-26
branch instruction execution times
Bus
packet format
recommended pinout 30-45
register accesses
serial interface 30-18
timing diagrams
BRA, Bcc instruction execution times (table 3-16) 2-32
table 3-15 2-32
access by matches in CSCR and DACR 13-4
characteristics 13-2
data transfer
electrical characteristics
features 13-1
internal
operands, misaligned 13-14
receive 30-18
transmit 30-19
EMAC 30-33
stack pointer 30-33
BDM serial port AC timing 33-28
real-time trace AC timing 33-28
back-to-back cycles 13-9
burst cycles 13-10
cycle execution 13-3
cycle states 13-4
fast termination cycle 13-8
read cycle 13-6
write cycle 13-7
input timing specifications 33-11
output timing specifications 33-12
arbitration 8-7
MPARK 8-9
allowable line access patterns 13-10
line read bus cycles 13-10
line transfers 13-10
line write bus cycles 13-12
algorithms 8-9
fixed mode 8-9
overview 8-8
round-robin mode 8-9
Index-1