MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 417

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following
expression:
22.4.3
The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time
between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer
and the beginning of the next, are both independently programmable.
The chip select to clock delay enable bit in the command RAM, QCR[DSCK], enables the programmable
delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD] determines the
period of delay before the leading edge of QSPI_CLK. The following expression determines the actual
delay before the QSPI_CLK leading edge:
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period
is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period
from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can
be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive
transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the
user can choose to delay a standard period after serial transfer is complete or can specify a delay period.
Writing a value to QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard
delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to
calculate the delay when DT equals 1:
Freescale Semiconductor
Table 22-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate
Transfer Delays
Delay after transfer
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
QMR[BAUD]
QSPI_CS-to-QSPI_CLK delay
QMR [BAUD]
255
16
32
2
4
8
=
Internal Bus Clock = 80 MHz
-----------------------------------------------------------------------------------
2
=
×
32
----------------------------------------------- -
[desired QSPI_CLK baud rate]
×
QDLYR[DTL]
f
sys
=
f
sys
QDLYR[QCD]
------------------------------------ -
QSPI_CLK
f
156.9 kHz
sys
2.5 MHz
20 MHz
10 MHz
1.25 Hz
5 MHz
(DT = 1)
Queued Serial Peripheral Interface (QSPI)
Eqn. 22-1
Eqn. 22-2
Eqn. 22-3
22-13