MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 233

IC MPU 32BIT COLDF 256-MAPBGA

MCF5214CVF66

Manufacturer Part Number
MCF5214CVF66
Description
IC MPU 32BIT COLDF 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet

Specifications of MCF5214CVF66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Package
256MA-BGA
Device Core
ColdFire
Family Name
MCF521x
Maximum Speed
66 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
142
Interface Type
QSPI/UART/I2C/CAN
On-chip Adc
8-chx10-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5214CVF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5214CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
13.4.6
The processor runs back-to-back bus cycles whenever possible. For example, when a longword read is
started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back
accesses are distinguished by the continuous assertion of TIP throughout the cycle.
read back-to-back with a write.
Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type
of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable.
Freescale Semiconductor
A[31:0], SIZ[1:0]
A[31:0], SIZ[1:0]
CSn, BSn
CLKOUT
Back-to-Back Bus Cycles
D[31:0]
CSn, BSn
R/W
CLKOUT
OE
TIP
TS
TA
D[31:0]
R/W
TIP
TS
TA
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 13-10. Write Cycle with Fast Termination
Figure 13-11. Back-to-Back Bus Cycles
S0
S1
S0
S2
S3
Read
S1
S4
S4
S5
Write
S0
S5
S1
S2
Write
External Interface Module (EIM)
S3
Figure 13-11
S4
S5
shows a
13-9

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