MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 406

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Queued Serial Peripheral Interface (QSPI)
22.1.2
The queued serial peripheral interface module provides a serial peripheral interface with queued transfer
capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between
transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers.
22.1.3
Features include:
22.1.4
Because the QSPI module only operates in master mode, the master bit in the QSPI mode register
(QMR[MSTR]) must be set for the QSPI to function properly. If the master bit is not set, QSPI activity is
indeterminate. The QSPI can initiate serial transfers but cannot respond to transfers initiated by other QSPI
masters.
22.2
The module provides access to as many as 15 devices with a total of seven signals: QSPI_DOUT,
QSPI_DIN, QSPI_CLK, QSPI_CS[3:0].
Peripheral chip-select signals, QSPI_CSn, are used to select an external device as the source or destination
for serial data transfer. Signals are asserted when a command in the queue is executed. More than one
chip-select signal can be asserted simultaneously.
Although QSPI_CSn signals function as simple chip selects in most applications, up to 15 devices can be
selected by decoding them with an external 4-to-16 decoder.
22-2
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Programmable queue to support up to 16 transfers without user intervention
— 80 bytes of data storage provided
Supports transfer sizes of 8 to 16 bits in 1-bit increments
Four peripheral chip-select lines for control of up to 15 devices (All chip selects may not be
available on all devices. See
are pinned-out.)
Baud rates from 156.9 Kbps to 20 Mbps at 80 MHz internal bus frequency
Programmable delays before and after transfers
Programmable QSPI clock phase and polarity
Supports wraparound mode for continuous transfers
External Signal Description
Overview
Features
Modes of Operation
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to
prior to configuring the QSPI module.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Chapter 14, “Signal Descriptions,”
Chapter 26, “General Purpose I/O
NOTE
for details on which chip-selects
Module”)
Freescale Semiconductor