MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 743

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

B.4
B.5
B.6
Freescale Semiconductor
Table 25-17/25-29 Added the following information to BITERR and ACKERR descriptions: “To clear this bit, first read it as a
Table 25-17/25-30 Changed bit ordering: ERRINT should be bit 2 and BOFFINT should be bit 1.
Table 33-8/33-9
Table 6-10/6-15
Table 17-2/17-5
Figure 4-2/4-6
Figure 6-3/6-6
25.4.10/25-16
Table 4-6/4-9
Table 4-6/4-9
17-23/17-39
Chapter 33
10.3.2/10-8
Title Page
Location
Location
Location
Figure
Changes Between Rev. 2 and Rev. 2.1
Changes Between Rev. 2.1 and Rev. 2.2
Changes Between Rev. 2.2 and Rev. 2.3
Changed bit 23 from DIDI to DISI
Under ‘Configuration’ for ‘Instruction Cache’ the ‘Operation’ entry changed to “Invalidate 2 KByte data
cache”
Under ‘Configuration’ for ‘Data Cache’ the ‘Operation’ entry changed to “Invalidate 2 KByte instruction
cache”
Changed bit 8 to write-only instead of read/write
Removed “selected by BKSL[1:0]” as these are internal signal names not necessary for end-user.
Added note after register descriptions: ‘If an interrupt source is being masked in the interrupt controller
mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the status register
(SR[I]) is set to a value lower than the interrupt’s level, a spurious interrupt may occur. This is because by
the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious
interrupt is generated because the CPU cannot determine the interrupt source. To avoid this situation for
interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before
setting the mask in the IMR or the module’s interrupt mask register. After the mask is set, return the
interrupt mask in the status register to its previous value. Since level seven interrupts cannot be disabled
in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level
seven interrupts is not recommended.
In PALR/PAUR entry, deleted “(only needed for full duplex flow control)”
Changed FRSR to read/write instead of read-only
Changed CANICR to ICRn
Added Power Spec info to Electricals chapter
Added MCF5280 to “Devices Supported” list on the title page.
Deleted reference to “TA=TL to TH”
one, then write it as a one. Writing zero has no effect.”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table B-5. Rev. 2.1 to Rev. 2.2 Changes
Table B-6. Rev. 2.2 to Rev. 2.3 Changes
Table B-4. Rev. 2 to Rev. 2.1 Changes
Description
Description
Description
Revision History
B-7