MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 415

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

22.4.1
The QSPI contains an 80-byte block of static RAM that can be accessed by the user and the QSPI. This
RAM does not appear in the device memory map, because it can only be accessed by the user indirectly
through the QSPI address register (QAR) and the QSPI data register (QDR). The RAM is divided into
three segments with 16 addresses each:
The transmit data and command RAM are user write-only. The receive RAM is user read-only.
Figure 22-10
The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate
locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the
value in QAR to increment. Correspondingly, a read from QDR returns the data in the RAM at the address
specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
22.4.1.1
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM
space. Read this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in
Freescale Semiconductor
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•
•
Receive data RAM—the initial destination for all incoming data
Transmit data RAM—a buffer for all out-bound data
Command RAM—where commands are loaded
QSPI RAM
Receive RAM
shows the RAM configuration. The RAM contents are undefined immediately after a reset.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Address
Relative
Figure 22-10. QSPI RAM Model
0x0F
0x1F
0x2F
0x00
0x01
0x10
0x11
0x20
0x21
...
...
...
Register
QRR15
QCR15
QTR15
QRR0
QRR1
QCR0
QCR1
QTR0
QTR1
...
...
...
Transmit RAM
16 bits wide
Receive RAM
16 bits wide
Command RAM
8 bits wide
Function
Queued Serial Peripheral Interface (QSPI)
22-11