MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 551

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Freescale Semiconductor
Bit(s)
12–8
7–0
15
14
13
MQ1[12:8]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Name
MQ1n
SSE1
CIE1
PIE1
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Disabled mode, conversions do not occur
Software-triggered single-scan mode (started with SSE1)
External-trigger rising-edge single-scan mode
External-trigger falling-edge single-scan mode
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Interval timer single-scan mode: time = QCLK period × 2
Externally gated single-scan mode (started with SSE1)
Queue 1 completion interrupt enable. Enables an interrupt request upon completion
of queue 1. The interrupt request is initiated when the conversion is complete for the
last CCW in queue 1.
1 Enable queue 1 completion interrupt.
0 Disable queue 1 completion interrupt.
Queue 1 pause interrupt enable. Enables an interrupt request when queue 1 enters
the pause state. The interrupt request is initiated when conversion is complete for a
CCW that has the pause bit set.
1 Enable the queue 1 pause interrupt.
0 Disable the queue 1 pause interrupt.
Queue 1 single-scan enable. Enables a single-scan of queue 1 after a trigger event
occurs. SSE1 may be set during the same write cycle that sets the MQ1 bits for one
of the single-scan queue operating modes. The single-scan enable bit can be written
to 1 or 0, but is always read as a 0, unless the QADC is in test mode. The QADC clears
SSE1 when the single-scan is complete.
1 Allow a trigger event to start queue 1 in a single-scan mode.
0 Trigger events are ignored for queue 1 single-scan modes.
Selects the operating mode for queue 1.
which enable different queue 1 operating modes.
Reserved, should be cleared.
Table 28-6. QACR1 Field Descriptions
Table 28-7. Queue 1 Operating Modes
Operating Mode
Description
Table 28-7
Queued Analog-to-Digital Converter (QADC)
7
8
9
10
11
12
13
14
15
16
17
shows the bits in the MQ1 field
28-13