EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 176

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

6
VICxVectAddr
6-14
Vectored Interrupt Controller
EP93xx User’s Guide
31
15
Definition:
Bit Descriptions:
Address:
Definition:
Note: Reading from this register provides the address of the ISR, and indicates to the priority
Note: If you are using the VIC and a program/debugger ever reads address VIC_BASE + 0x30,
30
14
• The ISR reads the VICxVectAddr register when an IRQ interrupt is generated
• At the end of the ISR, the VICxVectAddr register is written with any value in order to
update the priority hardware.
hardware that the interrupt is being serviced. Writing to this register indicates to the
priority hardware that the interrupt has been serviced. The register should be used as
follows:
a value must be written to VIC_BASE + 0x30. If not, only higher priority interrupts are
enabled and there are no higher priority interrupts. Therefore, no more interrupts will
occur. If you use the VIC in Vectored Interrupt mode, this is not an issue.
29
13
28
12
Protection Enable Register. The VICxProtection register enables or disables
protected register access. If the bus master cannot generate accurate
protection information, leave this register in its reset state to allow User mode
access.
VIC1VectAddr: 0x800B_0030 - Read/Write
VIC2VectAddr: 0x800C_0030 - Read/Write
Vector Address Register. The VICxVectAddr register contains the Interrupt
Service Routine (ISR) address of the currently active interrupt.
Reading or writing to the register at other times can cause incorrect operation.
RSVD:
Protection:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Enables or disables protected register access. When
enabled, only Privileged mode accesses (reads and
writes) can access the interrupt controller registers. When
disabled, both User mode and Privileged mode can
access the registers. This bit is cleared to ‘0’ on reset, and
can only be accessed in Privileged mode.
24
VectorAddr
VectorAddr
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0