EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 513

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
13.9 Registers
Boot Option
(ASDO)
The Synchronous Memory controller has seven registers as shown in
Configuration registers allow software to specify the operating parameters of the
Synchronous Memory controller according to the memory device types being used. The
Refresh Timer register allows software to specify the time period between successive
synchronous memory refresh commands. The Boot Status allows software to determine the
state of the boot configuration pins.
X
X
X
1
0
0x8006_000C
0x8006_001C
0x8006_0000
0x8006_0004
0x8006_0008
0x8006_0010
0x8006_0014
0x8006_0018
Address
A31
Table 13-13. Synchronous Memory Controller Registers
0
1
1
1
1
Table 13-12. Address Bits Used for Chip Select
Reserved
"GlConfig"
"RefrshTimr"
"BootSts"
"SDRAMDevCfg[3:0]"
(See Below)
SDRAMDevCfg[3:0]
SDRAMDevCfg[3:0]
SDRAMDevCfg[3:0]
SDRAMDevCfg[3:0]
Copyright 2007 Cirrus Logic
A30
0
1
1
1
1
Name
A29
0
1
1
0
0
Global Configuration
Refresh Timer
Boot Configuration Pins Status
Synchronous Device Configuration 0
Synchronous Device Configuration 1
Synchronous Device Configuration 2
Synchronous Device Configuration 3
SDRAM, SyncROM, and SyncFLASH Controller
Description
A28
0
1
0
1
0
Table
EP93xx User’s Guide
13-13. The
Chip select
nSDCS3
nSDCS3
nSDCS2
nSDCS1
nSDCS0
13-17
13