EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 588

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

16
UART3ModemCtrl
16-12
UART3 With HDLC Encoder
EP93xx User’s Guide
31
15
Default:
Definition:
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x0000_0000
UART3 DMA Control Register
RSVD:
DMAERR:
TXDMAE:
RXDMAE:
0x808E_0100 - Read/Write
0x0000_0000
Modem Control Register. Only the OUT1 and OUT2 bits have functionality in
UART3. The RTS and DTR bits exist but have no function.
RSVD:
OUT2:
OUT1:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If 1,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TX DMA interface enable. Setting to 1 enables the private
DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to 1 enables the private
DMA interface to the receive FIFO.
Reserved. Unknown During Read.
OUT2 function. Controls the TENn output behavior:
1 = TENn is driven by the UART3Flag.BUSY status bit;
that is, TENn is low whenever the UART has transmit data
to send.
0 = TENn is controlled by the OUT1 bit.
OUT1 function. When OUT2 = “0”, then TENn = OUT1.
Otherwise OUT1 is ignored.
24
8
RSVD
23
7
22
6
0
21
5
RSVD
20
4
OUT2
19
3
OUT1
18
2
17
1
DS785UM1
RSVD
16
0