EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 800

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

28
Register Descriptions
PxDR
28-10
GPIO Interface
EP93xx User’s Guide
31
15
Address:
30
14
1. A read from the data register returns the value of the GPIO module input port. These ports have a
default pin assignment. The read value default is the pin state based on the default pin map.
2. Port E bits 1 and 0 provide the LED driver function. The Port E[1:0] defaults to drive high. A read from
the Port E data register would be expected to return 0x03, if the other pins mapped to Port E inputs are
zero. However since the Port E[7:2] inputs are mapped to IDE control signals, the default read value will
depend on the default action of the IDE controller and the external interface.
3. The RAWSTATUSx registers have pin dependent default read states. The interrupt control registers
default to low level sensitive interrupt on reset. Therefore the external pin state will ripple through the
interrupt logic to determine the RAWSTATUSx default.
0x8084_00AC
0x8084_00BC
0x8084_005C
0x8084_009C
0x8084_00C0
0x8084_00C4
0x8084_00C8
0x8084_0050
0x8084_0054
0x8084_0058
0x8084_0060
0x8084_0064
0x8084_0090
0x8084_0094
0x8084_0098
0x8084_00A0
0x8084_00A4
0x8084_00A8
0x8084_00B0
0x8084_00B4
0x8084_00B8
29
13
Address
28
12
RSVD
27
11
Reserved, Read undefined
Read Location
26
10
GPIOAIntType1
GPIOAIntType2
GPIOBIntType1
GPIOBIntType2
GPIOFIntType2
Table 28-5. GPIO Register Address Map (Continued)
GPIOFIntEn
GPIOAIntEn
GPIOBIntEn
RawIntStsF
RawIntStsA
RawIntStsB
GPIOFDB
GPIOADB
GPIOBDB
EEDrive
IntStsF
IntStsA
IntStsB
25
-
-
9
Copyright 2007 Cirrus Logic
24
8
RSVD
23
7
Write Only
Write Only
Write Only
Read only
Read only
Read only
Read only
Read only
Read only
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
22
6
21
5
Write Location
GPIOAIntType1
GPIOAIntType2
GPIOBIntType1
GPIOBIntType2
GPIOFIntType2
20
4
GPIOFIntEn
GPIOAIntEn
GPIOBIntEn
GPIOFEOI
GPIOAEOI
GPIOBEOI
GPIOFDB
GPIOADB
GPIOBDB
PxDATA
EEDrive
-
-
-
-
-
-
19
3
18
2
Reset Value
Note 3
Note 3
Note 3
17
1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DS785UM1
-
-
16
0