EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 364

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
GlIntSts
9-62
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
INT
31
15
Address:
Chip Reset:
Soft Reset:
30
14
29
13
28
12
RxROI:
MIIII:
PHYI:
TI:
AHBE:
OTHER:
TxSQ:
RxSQ:
0x8001_0060 - Read/Write
0x0000_0000
0x0000_0000
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
When a runt frame is received with a CRC error, the
RxRuntCnt register is incremented, when the MSB of the
count is set, the RuntOv bit is set in the Interrupt Status
Register. If the RxROIE bit is set, an interrupt will be
generated.
The MII Status bit is set whenever a management
operation on the MII bus is completed.
The PHY Status bit is set when the MAC detects a change
of status event in the PHY.
The Timeout bit is set when the general timer (GT) count
register reaches zero.
This bit is set if a MAC generated AHB cycle terminated
abnormally. The Queue ID bits (Bus Master Status) will
indicate the DMA Queue which was active when the abort
occurred. DMA operation is halted on all queues until this
bit is cleared, and the queues are restarted via the Bus
Master Control register.
This bit is set when a status other than that covered by bits
10, 3 and 2 is present.
This bit is set when a status affecting the transmit status
queue has been posted.
This bit is set when a status affecting the receive status
queue has been posted. This bit can only be set if bit 2
(REOFIE), bit 1 (REOBIE) and bit 0 (RHDRIE) of the
Interrupt Enable (IntEn) register are set (enabled).
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0