EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 769

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
Address:
Default:
Definition:
Bit Descriptions:
0x808F_0000
0x0000_0000
Key scan initialization register.
RSVD:
DBNC:
DIS3KY:
DIAG:
BACK:
T2:
NA:
Copyright 2007 Cirrus Logic
Reserved. Unknown during read.
De-bounce start count. This value is used to pre-load the
de-bounce counter. The de-bounce counter counts the
number of consecutive scans that decoded the same
keys. Terminal count for the de-bounce counter is 0xFF.
Terminal count indirectly generates a key scan interrupt. A
pre-load value of 0xFC will cause the key scan circuitry to
count 3 identical consecutive keypad scans.
Disable 3 Key reset. Setting this bit high disables the three
key reset output to the watchdog reset block. Setting it
back low re-enables it.
Key scan diagnostic mode. Setting this bit high allows key
scanning to be directly controlled through the key register
by writes from the ARM Core. The DIAG.KEY[5:0] value is
written by the ARM Core. Then the KeyRegister.K bit is
read to determine if there is a key press. The result from
reading the KeyRegister.K bit is not hardware de-bounced.
Key scan back driving enable. Setting this bit high enables
the key scanning logic to back drive the row and column
pins of the chip high during the first two column counts in
the row/column counter.
Test mode bit. When this bit is set to “1”, the counter
RC_COUNT is advanced by 8 counts when EN is active.
The effect is that only column 0 is checked in each row.
This test mode allows a faster test of the ROW pins.
Not Assigned. These bits will read back the value written.
EP93xx User’s Guide
Keypad Interface
26-7
26