EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 312

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
9-10
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.1.4.7 Flow Control
9.1.4.8 Receive Flow Control
9.1.4.9 Transmit Flow Control
The relationship of RXCtl.MA and RXCtl.IAHA is shown below.
The MAC provides special support for flow control by the transmission and reception of
pause frames. A pause frame is a specific format of a MAC control frame that defines an
amount of time for a transmitter to stop sending frames. Sending pause frames thereby
reduces the amount of data sent by the remote station.
The MAC can detect receive pause frames and automatically stop the transmitter for the
appropriate period of time. To be interpreted as a pause frame the following conditions must
be met:
If accepted as a pause frame, the pause time field is transferred to the Flow Control Timer
register. The pause frame may be optionally passed on to the Host or discarded by the MAC.
Once the Flow Control Timer is set to a non-zero value, no new transmit frames are started,
until the count reaches zero. The counter is decremented once every slot time while no frame
is being transmitted.
When receive congestion is detected, the driver may want to transmit a pause frame to the
remote station to create time for the local receiver to free resources. As there may be many
frames queued in the transmitter, and there is a chance that the local transmitter is itself
being paused, an alternative method is provided to allow a pause frame to be transmitted.
Setting the Send Pause bit in the Transmit Control register causes a pause frame to be
transmitted at the earliest opportunity. This occurs either immediately, or following the
completion of the current transmit frame. If the local transmitter is paused, the pause frame
will still be sent, and the pause timer will still be decremented during the frame transmission.
• Destination address accepted by one of the first two individual address filters, with the
• The Type field must match that programmed in the Flow Control Format register.
• The next two bytes of the frame (MAC Control Opcode) must equal 0x0001.
• The frame must be of legal length with a good CRC.
appropriate RXCtl.RxFCE bit set.
RXCtl.MA
0
1
0
1
RXCtl.IAHA[0]
Table 9-2. RXCtl.MA and RXCtl.IAHA[0] Relationships
0
0
1
1
Copyright 2007 Cirrus Logic
Hash filter not used in acceptance criteria.
All multicast frames (first bit of DA = 1) passing the hash are
accepted.
All individual address frames (first bit of DA = 0) passing the hash
are accepted.
All frames that pass the hash are accepted.
Hash Filter Acceptance Results
DS785UM1